1. Field of the Invention
The present invention generally relates to a circuit for sensing a memory cell and, more particularly, to a circuit for sensing a multi-level cell.
2. Description of the Related Art
A multi-level cell (MLC) refers to one having a plurality of threshold voltages. To sense an MLC, a sensing circuit may traditionally employ an output signal from a sense amplifier to control the on/off state of a switch in order to decide whether to read data bits from a counter.
FIG. 1 is an exemplary circuit diagram of a sensing circuit 10 for sensing an MLC in prior art. Referring to FIG. 1, the sensing circuit 10 may include a sense amplifier 11, a delay unit 12, a logic “AND” gate 13, a first switch 14-1 and a second switch 14-2.
The sense amplifier 11 compares a threshold voltage of an MLC 18 with a word line voltage VWL. If the threshold voltage is smaller than VWL, the sense amplifier 11 provides a signal of logic 0 (zero). On the other hand, if the threshold voltage is greater than VWL, the sense amplifier 11 provides a signal of logic 1 (one).
When the output of the sense amplifier 11 is logic 0, the AND gate 13 outputs logic 0, which turns off the switches 14-1 and 14-2. Accordingly, data bits DB[1] and DB[0] are blocked. When the output of the sense amplifier 11 is logic 1, the AND gate 13 outputs logic 1, which turns on the switches 14-1 and 14-2. The data bits DB[1] and DB[0] are then allowed to pass through buffers 17-1 and 17-2, latch units 15-1 and 15-2, and inverters 16-1 and 16-2, and are read as RB[1] and RB[0], respectively.
The sensing circuit 10 may suffer a read margin issue due to a relatively small signal width of a switch turn-on signal. Furthermore, the buffers 17-1 and 17-2 may consume a large chip area and thus are not desired.